The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for a non-volatile memory device including a channel region for providing carriers to a second channel region for injecting into the floating gate. Merely by way of example, the invention has been applied to embedded non-volatile memory devices having high programming efficiency and low erase voltage. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuits for stand-alone non-volatile memories or memory card applications.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is non-volatile memory devices for the manufacture of integrated circuits in a cost effective and efficient way.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor International Manufacturing Company (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, as logic devices are scaled and designed to operate under lower voltages, non-volatile memory devices are difficult to scale down and continue to need high voltages to operate.
For example, a conventional stacked gate non-volatile memory device requires only a single transistor for each cell, but it requires high programming current which makes it difficult to utilize on-chip high voltage generation for programming and erase. A conventional split gate non-volatile memory device is a single transistor electrically programmable and erasable memory cell. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate. Programming is accomplished by electrons from the source migrating through the channel region underneath the control gate and then by abrupt potential drop injecting through the first insulating layer into the floating gate. This device can suffer from difficulty in further scaling down and low manufacturability yield. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.